Semiconductor memories in recent years are required to have added high values such as a high access speed and various operation modes. For example, a dynamic random access memory (DRAM) has two operation modes, i.e., a normal read/write operation mode based on an external address signal and a refresh operation mode based on an internal address signal provided by an address counter disposed on a chip. The DRAM must speedily decode these address signals for the operation modes.
The DRAM comprises, for example, memory cells, sense amplifiers, a column decoder, a word driver, a row address buffer, a clock generator, a mode decision circuit, and a switching circuit.
A normal read/write operation of the DRAM will be explained. The clock generator provides a control signal, according to which an address latch circuit in a buffer cell latches an external address signal through an input terminal thereof. The mode decision circuit determines an operation mode, and according to the determination, data of the external address signal latched by the address latch circuit is transferred to a row decoder through an address bus. The row decoder decodes the transferred data and provides the word driver with the decoded address to select a word line. Next, a refresh operation will be explained. The clock generator similarly provides a control signal, according to which the address latch circuit of the buffer cell latches an external address signal supplied to the input terminal. The mode decision circuit determines an operation mode, and according to the determination, data of an internal address signal is transferred to the row decoder to similarly select a word line.
To reset the chip, a selected word line is reset at first according to a reset signal. Then, the clock generator 86 changes the control signal, and in response to the change, the mode decision circuit provides a mode signal of predetermined level, which causes the switching circuit to change switching control signals. As a result, signal lines of the address bus and then the decoded address are reset.
In this way, according to the conventional row-system controller, the external or internal address signal is provided to the address bus only after the mode decision circuit determines an operation mode according to row address and column address strobe signals and after the operation mode signals are set to a level indicative of the operation mode. Accordingly, the conventional semiconductor memory has problems of extending a decoding time and slowing an access speed. When resetting the chip, a selected word line must be discharged at first before resetting an address bus for the word line and a decoded address. This makes it difficult to shorten a reset time and cycle time.